The present invention is related to the field of communications. More particularly, the present invention is a system and method for high efficiency, high performance parallel processing of turbo codes.
Turbo coding is a recently developed forward error correction coding and decoding technique that provides previously unavailable error correction performance. A general description of a parallel turbo code can be found in U.S. Pat. No. 5,446,747 entitled xe2x80x9cError-correction Coding Method With at Least Two Systematic Convolution Codings in Parallel, Corresponding Iterative Decoding Method, Decoding Module and Decoder,xe2x80x9d filed Apr. 16, 1992 assigned to France Telecom and incorporated herein by reference. The enhanced level of error correction provided by turbo codes facilitates the transmission of data over noisy channels, thereby improving the data transmission capability of all sorts of communications systems.
Some characteristics of turbo codes combine to make the associated decoders more difficult to implement in an integrated circuit. These characteristics include large frame sizes, the use of repeated decoding steps that incorporate extrinsic information, and the use of a pseudo random interleaver for generating interleaved versions of the transmitted information and extrinsic information used during encoding and decoding. Additionally, many turbo-coding schemes require a sufficiently high degree of randomness in the psuedo random interleaver such that the sequence must be stored in memory rather than calculated on the fly.
This combination of characteristics causes turbo codes to require, in general, greater processing resources than other forward error correction coding techniques. For example, the use of repeated decoding steps increases the decoding time. The (typically) large frame size combined with the use of extrinsic information during decoding increases the amount of memory required to implement a decoder.
Additionally, the use of a pseudo random interleaver complicates the ability to decode a frame in parallel because extrinsic and sample information can not be accessed in an orderly fashion. Memory requirements are further increased by the use of memory based interleavers, which are preferred when turbo codes having the best performance are required. The use of memory based interleavers can also reduce the speed of the decoder since the interleaver typically has to be accessed twice during a decoding subiteration. This limits the possible decoding speed to half the memory access rate, which is often much slower than the rate of other available circuits.
The present invention is directed to providing a decoding circuit that minimizes the negative effect the above described characteristics have on performance and cost, thereby increasing the number of applications for which turbo codes may be used in a practical and economic manner. Additionally, the present invention is directed to a turbo decoder architecture that provides broadband capability using a practical amount of circuitry and memory.